Firmware Design Engineers - DSP & VHDL

Firmware Design Engineers x 2+ 12 month contracts+ Up to 75 per hour+ Portsmouth basedKey Skills:Understanding of DSPVHDL Encoding to a high standard in a Linux environmentLinux experience.Verilog / SystemVeriloXilinx Vivado experience, particularly use of block diagrams and non-project modeYou will join our Modems and Software Defined Radio group and report to the Engineering Manager of the project, delivering a...

Pawhut 1.21M Cat Tree Tower With Sisal Scratching Posts Bed Tunnel Perch Teaser Toy - Brown D30-288V01bn

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NON STARTER, SELLING FOR PARTS. Rover 25, Hatchback, 2003, Manual, 1396 (cc), 5 doors

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Product Specifications

General
gs	CBSbutler Holdings Limited trading as CBSbutler
Posted	8 days ago
description	Firmware Design Engineers x 2 + 12 month contracts + Up to 75 per hour + Portsmouth based Key Skills: Understanding of DSP VHDL Encoding to a high standard in a Linux environment Linux experience. Verilog / SystemVerilo Xilinx Vivado experience, particularly use of block diagrams and non-project mode You will join our Modems and Software Defined Radio group and report to the Engineering Manager of the project, delivering a new product to the UK MOD. Mandatory Skills: Understanding of DSPVHDL Encoding to a high standard in a Linux environmentXilinx Vivado experience, particularly use of block diagrams and non-project modetcl scripts for configuring and connecting IP and building projects in the Vivado environmentVerilog / SystemVerilogGit for version controlAtlassian toolset (e.g. Jira, Confluence, BitBucket)Agile or Scrum working environmentBeneficial Skills: Familiarity with Zynq Ultrascale RFSoCs e.g. use of AXI busses, associated IPMakefile, Linux shell, Jenkins Control scriptsSystem and software modelling tools such as Enterprise Architect (SysML / UML)Python for test purposesSDR (Software Defined Radio)
location	Portsmouth, Hampshire